A Cleaner Alternative to Slurry-Based Polishing for PIC Edge Preparation

May 15, 2026, 6:09 p.m.

1. Introduction: The Challenges of PIC Edge Processing

In Photonic Integrated Circuit (PIC) manufacturing, the transition from wafer-level processing to device packaging hinges on the quality of edge preparation. High-precision facet processing is mandatory to expose waveguides and ensure the sub-micron alignment required for interconnect compatibility. Traditional Chemical Mechanical Polishing (CMP) is often the default for wafer thinning; however, it introduces significant technical liabilities when applied to edge processing, specifically regarding variability and material removal limits.

Process evaluations confirm that dry mechanical polishing serves as a technically superior alternative for waveguide exposure. It is essential to clarify that "dry" in this context refers to a slurry-free environment, eliminating the abrasive chemical suspensions typical of CMP, while utilizing water-cooled and lubricated lapping films as a coolant. This approach provides the precise material removal and surface integrity necessary for high-yield PIC production.

2. Comparative Analysis: Slurry-Free Mechanical Polishing vs. CMP

The shift from CMP to slurry-free mechanical polishing directly addresses the primary bottlenecks in PIC edge preparation: process variability and post-polishing contamination.

Operational Efficiency and Repeatability

By eliminating slurries, engineers can effectively mitigate the "black box" variables of chemical concentration and suspension settling. Engineering data shows that this transition reduces operating costs by removing the need for intensive post-process cleaning stations and hazardous waste management. Furthermore, mechanical polishing provides deterministic control over the facet via programmable logic, ensuring that edge geometry remains consistent across multiple production batches.

Dry Mechanical Polishing vs. CMP Polishing

3. Precision Material Removal and Chipping Mitigation

A fundamental failure point in using CMP for PIC edges is its inability to manage dicing-induced damage. While CMP excels at removals under 5 µm, standard wafer dicing typically generates chips and micro-cracks ranging from 5 µm to several hundred microns.

Technical strategy dictates a "dicing-plus-polishing" workflow: waveguides should be intentionally recessed during the dicing phase to avoid catastrophic damage to light-carrying features. Mechanical polishing then recovers the device by "polishing out" dicing damage and exposing the waveguides with micron-level accuracy. Laboratory testing confirms the NOVA system’s capability to remove up to 250 µm of material per side, effectively recovering chips that would otherwise be scrapped due to poor dicing quality.

Tribological Insight: Process data indicates that the microfeed rate is critical to mitigating chipping. Optimal results were achieved at a rate of 0.01 mm per 4 seconds. Notably, engineering observations showed that slower feed rates actually increased chipping in coarser films, a counter-intuitive finding that highlights the importance of maintaining proper diamond grit engagement.

4. Surface Finish and Optical Performance

While high-capacity material removal is required to clear dicing damage, the final surface must meet stringent optical specifications to minimize scattering and optimize insertion loss.

Using 0.02 µm SiO2 (XW) finishing film, process evaluations consistently achieve surface roughness values down to ~2 nm Ra. This surface quality is essential for fiber coupling, as it ensures the facet provides a high-fidelity optical interface. Strategic implementation of these final polishing steps allows the PIC to meet the rigorous performance metrics required by next-generation FAUs and interconnect devices.

5. Case Study: LiNbO3/SiO2/Si Chip Polishing

To validate these methodologies, extensive testing was performed on LiNbO3/SiO2/Si samples of varying widths (4mm and 5mm) with 22.2mm x 0.525mm facets.

Equipment and Process Parameters

Testing utilized the NOVA Geo™ Polishing System in conjunction with the NV-FLEX Workholder. Key engineering parameters included:

• Z-Axis Control: The system’s 5 µm Z-axis resolution enabled the fine pressure control required for both high-volume grinding and delicate finishing.
• Fixturing and Torque: To ensure stability for the long-axis (22.2mm) facet, a Z-Screw Clamp was implemented. This prevented "lifting" during the process. The clamp was set to a precise torque of 2 cN*m to secure the sample without inducing stress fractures.
• Surface Protection: A 5mil Teflon layer was placed on the chip base to protect the top surface of the PIC during downward-facing processing.

Recommended Film Progression

Based on the "LiNbO3/SiO2/Si Sample Testing Report," the most efficient sequence to balance material removal and chip reduction is:

1. Planarization/Grind: 6 µm Diamond film. (Testing confirmed 6 µm is superior to 9 µm, as the latter induced larger, less controllable chips).
2. Intermediate/Chip Reduction: 3 µm Diamond. Note: This is the most crucial transition phase. It is a "balanced" film that reduces defects carried over from the grind without inducing new chipping.
3. Fine Polish: Sequence of 1 µm and 0.5 µm Diamond films.
4. Final Finish: 0.1 µm Diamond or 0.02 µm SiO2 (XW), depending on specific Ra requirements.

Integrated Vision Synergy

The process utilizes a triple-videoscope setup to maintain referenced positions throughout the cycle:

• SV10: Confirms surface planarization and verifies progression.
• SV9: Ensures precision angle alignment.
• SV11 (Side View): This is the critical component for monitoring material removal limits in real-time. It allows the operator to stop the grind precisely when the waveguide is exposed, preventing over-polishing.

6. System Versatility and Scalability

The NOVA platform’s design supports a broad manufacturing strategy. A single system can transition from processing PIC facets to Fiber Array Units (FAUs), bare fibers, or standard connectors via a simple workholder swap. This versatility is vital for organizations where a single equipment platform must support R&D, pilot lines, and full-scale production groups, maximizing ROI while maintaining process continuity.

7. Technical Conclusion

Engineering evaluations confirm that slurry-free mechanical polishing is the most reliable method for PIC edge preparation. It provides the high-volume material removal (up to 250 µm) necessary to polish out dicing damage while maintaining a 5 µm Z-axis resolution for precision pressure control.

For maximum yield and repeatability, I recommend the implementation of integrated vision systems like the SV11. Real-time monitoring of material removal ensures that the waveguide facet is exposed with mathematical precision without disrupting the clamped reference points, thereby eliminating the rework and scrap typically associated with traditional manual or CMP-based edge processing.

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